1. Field of the Invention
The present invention relates generally to a semiconductor memory device. More specifically the invention relates to a semiconductor memory device having memory cells, each constituted of one flip-flop circuit and two switching transistors.
2. Description of the Related Art
Conventionally, as a static random access memory (hereinafter referred to as "SRAM") having memory cells, each constituted of one flip-flop circuit and two switching transistors, one having the following construction has been known.
FIG. 1 shows a circuit diagram of a SRAM cell. The SRAM cell is present at a junction between complementary data lines DL1 and DL2 and one set of word lines WL1 and WL2 and connected to the data lines and the word lines via switching transistors Qt1 and Qt2. Also, source regions of driver transistors Qd1 and Qd2 are connected to a grounding wiring Vss. Source regions of MOS type TFT Qp1 and Qp2 as load elements are connected to a power supply wiring Vcc.
FIG. 2 shows a section of such SRAM cell. In the construction illustrated in FIG. 2, the driver transistors Qd2, with commonly connected to a contact hole Cg2 connecting the source regions and the grounding wiring Vss, and a part of the driver transistor Qd2A and MOS type TFT Qp1 and Qp2 of another SRAM cell adjacent to the illustrated SRAM cell are illustrated.
Next, a fabrication process of the prior art will be discussed, At first, as shown in FIG. 3A, after forming a field oxide layer 2 for element isolation on a P-type silicon substrate 1 by selective oxidation, gate oxide layer 3 is formed on the substrate 1 by thermal oxidation.
Subsequently, the gate oxide layer 3 above regions that will form the drains of the driver transistors Qd1 and Qd2 is selectively removed to form a buried contact hole DC2.
Then, gate electrode 4(Qd2) of a polycrystalline silicon layer doped in N-type is formed. Thereafter, using the gate electrode 4 as mask, ion implantation for phosphorous is performed. By this, N-type low concentration diffusion layer 6, the source and drain regions of the driver transistors Qd1 and Qd2 and the switching transistors Qt1 and Qt2, is formed.
Subsequently, after formation of a spacer 7 formed of a silicon oxide layer on the side surface 4 of the gate electrode 4, ion implantation of arsenic is performed. By this, N-type high concentration diffusion layer 9, which is the source and drain regions of the driver transistors Qd1 and Qd2 and the switching transistors Qt1 and Qt2 is formed. It should be noted that the reference numeral 8d-2 represents a N-type high concentration diffusion layer of the buried contact hole DC2.
Then, as shown in FIG. 3B, after depositing interlayer insulation layer of silicon oxide, using a photoresist layer 18 as a mask, a contact hole Cg2 is formed in the source forming region of the driver transistors Qd1 and Qd2.
Thereafter, in order to suppress increasing of a contact resistance, ion implantation of phosphorous is performed for the surface of the substrate exposed within the contact hole Cg2. By this, N-type high concentration source region 10 is formed as shown in FIG. 3C. Subsequently, with a refractory silicide film 11 connected to the N-type high concentration source region 10, the grounding wiring 11 (Vss) is formed.
Then, as shown in FIG. 2, a silicon oxide layer as an interlayer insulation layer 12 is formed, a contact hole is formed above the gate electrode (such as 4(Qd1) and so forth) of the driver transistor, the gate electrode (13-1 and so forth) of the load element is formed, a TFT gate oxide layer 14 is formed, a TFT channel portion and so forth is formed by providing the contact hole, a BPSG layer 16 is deposited, and the data line 17 (D11) of an aluminum film 17 is formed by forming the contact hole for data line.
In FIG. 2, the contact hole Cg2 for grounding of the driver transistor is placed with offset from the center of the driver transistors Qd2 and Qd2A. This offset is caused by mask alignment for forming the contact hole Cg2. This offset may cause non-uniformity of the source region of the driver transistor. In the example of FIG. 2, the driver transistor Qd2 has the N-type low concentration diffusion region 6 whereas the driver transistor Qd2A does not have the N-type low concentration diffusion layer. Similar matter occurs on another driver transistor Qd1. Accordingly, unbalance in current drive performance is caused between two driver transistors in the same SRAM cell. For stable operation of the SRAM cell, it is essential that the performance ratio (on current ratio) of the driver transistor is higher than that of the switching transistor. Therefore, unbalance in the current driving performance should cause instability in the SRAM cell operation.
The above-mentioned SRAM thus encounters problems in that fluctuation in dimension between the high concentration source region and the gate electrode is easily caused and assuring stable operation is difficult. While such problems may be solved by providing greater interval to the adjacent memory cell, this solution is clearly backward in view of package density.